1. Field of the Invention
The present invention relates to an image pickup apparatus for superimposing a plurality of image signals one on another to display a plurality of reproduced scenes on one screen, and an image signal processing system.
2. Description of the Related Art
FIG. 8 is a block diagram of the schematic arrangement of an image signal processing circuit for superimposing an image signal providing an inset scene on another image signal providing a main scene, which circuit has been used by the inventors.
The circuit comprises a TV camera 1 for taking an image signal X.sub.(t) providing a main scene, the camera 1 being adapted to be actuated by a synchronization signal which is prepared in the camera itself. The image signal X.sub.(t) consists of such a synchronizing signal and an image component superimposed on the synchronizing signal. The circuit also comprises another TV camera 2 for taking an image signal Y.sub.(t) providing an inset scene. This inset scene camera is similarly actuated by a synchronizing signal which is generated in the inset scene camera itself. The image signal Y.sub.(t) also includes the synchronizing signal.
The image signals X.sub.(t) and Y.sub.(t) are respectively outputted from the TV cameras 1 and 2 which are independently actuated at different timings. Since these image signals are thus different in scan timing from each other, they cannot be superimposed one on another as they are. In order to overcome such a problem, the image signal processing circuit further comprises a scene control circuit 3 which causes the image signal Y.sub.(t) to be once stored in a field memory 4. The image signal Y.sub.(t) is then read out of the field memory 4 in accordance with the synchronizing signal in the image signal X.sub.(t). As a result, the scan timing of the image signal Y.sub.(t) will be consistent with that of the image signal X.sub.(t) . The synchronizing signal CS1 of the image signal X.sub.(t) is separated From the image signal X.sub.(t) at a synchronizing separation circuit 5 and then supplied to the scene control circuit 3.
On the other hand, the image signal Y.sub.(t) is divided into a synchronizing signal component CS2 and an image signal component y.sub.(t) at a synchronizing separation circuit 6. The image signal component y.sub.(t) is supplied to the scene control circuit 3 through an A/D converter 7 while the synchronizing signal CS2 is provided directly to the scene control circuit 3.
A digital image component is written in the field memory 4 in accordance (or in synchronism) with the synchronizing signal CS1. A digital image signal is read out from the field memory 4 in accordance with the synchronizing signal CS1 and then converted into an analog image signal y.sub.1(t) by a D/A converter 8, which signal is in turn fed to a synthesizing circuit 9.
The image signal y.sub.1(t) is one for forming an inset scene smaller than a main scene defined by the image signal X.sub.(t) and includes horizontal and vertical image signal components which are reduced by thinning or synthesizing any suitable number of bits from tile data of the image signal y.sub.1(t). The scene control circuit 3 generates a selection pulse SP in synchronism with the effective imaging period in the image signal y.sub.1(t), the selection pulse ST being then supplied to the synthesizing circuit 9. The synthesizing circuit 9 replaces the main scene image signal X.sub.(t) with the image signal component y.sub.1(t) in response to the selection pulse ST. In other words, the synthesizing circuit 9 is actuated by the selection pulse SP such that it will selectively output the image signal X.sub.(t) from the TV camera 1 or the image signal y.sub.1(t) from the D/A converter 8. In such a case, the image signal X is steadily selected, but the image signal y.sub.1(t) is selected only within its effective imaging period. In such a manner, there is provided an image signal Z.sub.(t) for displaying the inset scene of tile image signal y.sub.1(t) on a part of the main scene.
The position of the main scene at which the inset scene is displayed is determined by a timing at which the image signal y.sub.1(t) is outputted. It can be set by setting a delay on the output of the image signal y.sub.1(t) relative to the horizontal and vertical scan timings of the synchronizing signal CS.sub.1. For example, if the signal y.sub.1(t) is outputted with a delay relative to the horizontal scan timing of the synchronizing signal CS.sub.1, the position of the inset scene is moved on the main scene rightwardly. On the contrary, if another delay is provided relative to the vertical scan timing, the inset scene is moved on the main scene downwardly.
In such an arrangement, a part of the main scene can be replaced by an inset scene, the main and inset scenes being simultaneously displayed on one monitor screen.
However, such an arrangement is required to once store the image signal X.sub.(t) in the field memory 4. This additionally requires the A/D converter 7 for converting the image signal y.sub.(t) into a digital value and the D/A converter 8 for reconverting the digital value into tile image signal y.sub.1(t) . In general, the A/D and D/A converters 7, 8 used to process the image signals require special circuits for meeting their highspeed requirements, leading to increase of cost.
These converters also contributes to increase of the entire scale of the system. Thus, the A/D and D/A converters cannot be easily installed in any small-sized TV camera. This requires a separate unit for processing the image signals, Further leading to increase of manufacturing cost.